Method for compensating non-linearity of a sigma-delta analog-to-digital converter

ABSTRACT

The invention concerns a method for compensating the non-linearity of a sigma-delta analog-to-digital converter (A 2 ) with quantization at N levels comprising a digital-to-analog converter ( 24 ). The method comprises a calibrating step which consists in transforming the multibit sigma-delta analog-to-digital converter (A 2 ) into a sigma-delta analog-to-digital converter with quantization at three levels, then at two levels. The correction values of each level to be corrected are accurately measured. The method also comprises a normal functioning phase which consists, when the sigma-delta an analog-to-digital converter (A 2 ) is operating with quantization at N levels, in producing an instantaneous correction of errors of the analog-to-digital converter ( 24 ) using said correction values.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention concerns a method and a system for compensatingthe non-linearity of a sigma-delta analog-to-digital converter.

2. Description of the Related Art

Equipment in all fields, electronic or otherwise, consumer orprofessional, increasingly employs digital rather than analogprocessing. This choice is often justified by technical advantages thatare now well known, such as very stable parameters, excellentreproducibility of results, and increased functionality.

The external world being inherently analog, in most casesanalog-to-digital converters (ADC) and digital-to-analog converters(DAC) provide at some level the interface between the external world andthe digital core of the equipment.

The development of powerful digital processors has created a need for ahigh-resolution analog-to-digital converter compatible with CMOS VLSI(Very Large Scale Integration) technologies. The sigma-delta modulationconverter in particular has exploited technological developments.

As shown in FIG. 1, a sigma-delta analog-to-digital converter primarilyincludes an adder 1, a noise-shaping filter 4, a quantizer 5, a digitalfilter 6 and a feedback loop 8 connecting the output of the quantizer 5to the negative input 3 of the adder 1. The feedback loop 8 includes ananalog-to-digital converter 7. A sample-and-hold device (not shown),usually on the input side of the adder 1, oversamples the signal at agiven frequency and then maintains the level at the output 2 constant toenable the sigma-delta analog-to-digital converter to process the data.The noise-shaping filter 4 shapes the noise spectrum to attenuate thenoise power in the frequency range of the wanted signal. The quantizer 5employs a set of discrete levels and associates the closest discretelevel with the analog value at its input. This introduces an error knownas “quantizing noise”. The performance of a converter is conditioned bythe quantizing noise power. To this end, the oversampling performed inthe sample-and-hold device (not shown) and the feedback loop 8 “pushes”the maximum quantizing noise power out of the pass-band of the signal(the band of frequencies at which the system operates). The digitalfilter 6 at the output of the sigma-delta analog-to-digital converter,also known as a decimation filter, eliminates the shaped quantizingnoise and undersamples the output signal. The digital-to-analogconverter 7 has a transfer function that links the input (quantizing)digital levels delivered by the quantizer 5 to output analog values thatare then fed to the negative input 3 of the adder 1. Theanalog-to-digital converter 7 associates a corresponding analog outputvalue with each quantizing input level.

The fundamental principle of the sigma-delta analog-to-digital converterconsists firstly of oversampling the signal using the analogsample-and-hold device, pushing the quantizing noise power maximumoutside the pass-band of the signal, by integrating the quantizer into afeedback loop, and then filtering the signal obtained by means of adigital filter 6. These conjugate actions initially “dilute” thequantizing noise in a wide band thanks to the oversampling, shape thenoise spectrum, and then filter the quantizing noise to retain only thewanted band of the signal.

Using a multibit quantizer associated with a multibit digital-to-analogconverter in the feedback loop of a sigma-delta analog-to-digitalconverter is beneficial because it improves the signal/noise ratio anddynamic range of the sigma-delta analog-to-digital converter.

However, the performance of the sigma-delta analog-to-digital converteris highly dependent on the linearity of the sigma-deltaanalog-to-digital converter 7 used in the feedback loop 8.

One prior art solution that has been proposed for calibrating themultibit digital-to-analog converter regardless of the number of levelsis described by SARHANG-NEJAD and G. C. TEMES, “A High ResolutionMultibit Sigma Delta ADC with Digital Correction and Relaxed AmplifierRequirements”, IEEE Journal of solid state circuits, vol. 28, N 6, June1993, pages 648-660. It proposes to improve the performance of thesigma-delta analog-to-digital converter by measuring the non-linearitiesof the digital-to-analog converter 7 during a calibration phase. Duringthe calibration phase, the multibit sigma-delta analog-to-digitalconverter is converted into a one-bit sigma-delta analog-to-digitalconverter (only the most significant bit at the output of the quantizeris considered). The calibration phase essentially employs the componentsshown in FIG. 2, which shows the adder 1, the noise-shaping filter 4,the quantizer 5 and the decimation filter 6. The digital-to-analogconverter 7 is replaced by switching means Ea for imposing at thenegative input 3 of the adder 1 either a positive voltage Vref or anegative voltage −Vref, depending on the value of the output of theone-bit quantizer 5. The digital-to-analog converter 7 is then placed atthe positive input 2 of the adder 1. A counter Eb controls thedigital-to-analog converter 7 by feeding it a digital signal(corresponding to one of the levels available to the quantizer 5) sothat it generates an analog signal at the input of the one-bitsigma-delta analog-to-digital converter. An adder Ec receiving theoutput signal of the counter Eb and the output signal of the decimationfilter 6 calculates a correction value that is stored in a memory moduleEd. The counter Eb also controls addressing of the memory module Ed.

Each correction value represents a digital error caused by thedigital-to-analog converter 7 in converting between a digital value andits analog conversion. During the phase of normal use, the sigma-deltaanalog-to-digital converter is equivalent to that shown in FIG. 1 with adigital correction module (not shown) containing the correction valuesadded in front of the decimation filter 6. All digital values leavingthe quantizer 5 are corrected by the digital correction module beforereaching the decimation filter 6. Thus the corrected digital valueentering the decimation filter 6 is substantially equal to the analogvalue at the negative input 3 of the adder 1.

The above technique has a number of drawbacks, associated with themanner in which the correction values are measured. In the calibrationphase (FIG. 2), the output of the digital-to-analog converter 7 is fedto the positive input 2 of the adder 1, whereas under normal operatingconditions (FIG. 1 plus correction module) the digital-to-analogconverter 7 is in the feedback loop 8 and its output is fed to thenegative input 3 of the adder 1. The behavior of the digital-to-analogconverter 7 differs between the calibration phase and normal operatingconditions because the two inputs of the adder 1 are different. The twoinputs of the adder 1 do not have exactly the same capacitance, becauseit generally uses switched capacitors.

FIG. 3 shows an adder using switched capacitors. The switches 9, 10 and12, 13 respectively switch a capacitor C₁ and a capacitor C₂ which areconnected to a ground 14. The adder has two inputs E1 and E2respectively connected to the capacitors C₁ and C₂. An operationalamplifier 11 performs the addition operation by means of a feedbackcapacitor C. The capacitors C₁ and C₂ theoretically have the samecapacitance. However, in practice, because of manufacturing tolerances,their capacitances are different and the gain between the two inputs istherefore different.

During the calibration phase, the digital-to-analog converter istherefore connected to the input E1 and the values injected are measuredaccurately. During the normal operation phase, the digital-to-analogconverter included in the feedback loop is connected to the input E2 ofthe adder. Because the capacitors C1 and C2 are in practice different,the values measured during the calibration phase are therefore not infact the values injected during the normal operation phase. Also, theaccuracy of the measurement may be influenced by offset voltagesinherent to the sigma-delta analog-to-digital converter. The offsetvoltages may not be a problem during the normal operation phase, but canbecome a problem during the calibration phase because it entailsmeasuring DC voltages.

SUMMARY OF THE INVENTION

The invention aims to solve the above problem by retaining the structureof the sigma-delta analog-to-digital converter during the calibrationphase and using only digital signals.

The invention proposes a method of compensating the non-linearity of asigma-delta analog-to-digital converter with N quantizing levels andincluding a digital-to-analog converter in a feedback loop. N is aninteger greater than two. The method includes a normal operation phasein which a plurality of digital values corresponding to a plurality ofquantizing levels are modified by correction values Ci, where i is apositive integer from 1 to N, calculated during a calibration phase.According to a general feature of the invention, the correction valuesCi are calculated from values of the output of the sigma-deltaanalog-to-digital converter processed digitally with thedigital-to-analog converter retained in the feedback loop of thesigma-delta analog-to-digital converter and after converting themultibit sigma-delta analog-to-digital converter into a sigma-deltaanalog-to-digital converter with three quantizing levels, for examplemodifiable levels. The number N is a positive integer greater than 2.

The correction values C_(i) are used to correct errors caused by thedigital-to-analog converter. The corrections are preferably madeinstantaneously during the normal operation phase.

The method in accordance with the invention of compensatingnon-linearity includes a calibration phase during which the multibitsigma-delta analog-to-digital converter is converted into a sigma-deltaanalog-to-digital converter with three quantizing levels X_(m), X_(M)and X_(i), where i is from 1 to N−2; during a period P1 _(i), apredetermined value is delivered to the input of the sigma-deltaanalog-to-digital converter and the values from the output of thesigma-delta analog-to-digital converter are processed digitally; thiscalibration phase is executed N−2 times, retaining the levels X_(m) andX_(M), and taking successively for the level X_(i) the N−2 levels otherthan the levels X_(m) and X_(M). The correction values Ci of the N−2levels other than X_(m) and X_(M) are advantageously calculated usingthe processed values, the N−2 correction values C_(i) being adapted tomodify the N−2 levels other than X_(m) and X_(M) during the normaloperation phase.

The levels X_(m), X_(M) and X_(i) are digital values that are convertedinto analog values in accordance with a transfer function of thedigital-to-analog converter.

The method can further include, during the calibration phase and beforecalculating the correction values Ci, at least one step F during whichthe multibit sigma-delta analog-to-digital converter is converted into asigma-delta analog-to-digital converter with two quantizing levels X_(m)and X_(M). During a period P2, said predetermined value is delivered tothe input of the sigma-delta analog-to-digital converter, and thesuccessive values of the output of the sigma-delta analog-to-digitalconverter are processed digitally. In other words, step F advantageouslyeliminates any offset voltages in the sigma-delta analog-to-digitalconverter.

For example, if step F is performed only once, the periods P1 _(i) canall be equal to one another and equal to the period P2.

The calibration phase presupposes that X_(i) is different from X_(m) andX_(M).

In accordance with the invention the sigma-delta analog-to-digitalconverter with N quantizing levels is converted into a sigma-deltaanalog-to-digital converter with a number of quantizing levels less thanN by modifying quantizing threshold values and by digital processingusing internal comparators. In the general case the sigma-deltaanalog-to-digital converter with N quantizing levels is converted into asigma-delta analog-to-digital converter with three quantizing levels,and if the optional step F (offset voltage correction) is implemented,it is also converted into a sigma-delta analog-to-digital converter withtwo quantizing levels.

According to one advantageous feature of the invention, the levels X_(m)and X_(M) are respectively the minimum value and the maximum value ofthe N quantizing levels.

In one embodiment of the invention, during the normal operation phase,its correction value C_(i) is added to each level X_(i) present at theoutput of the quantizer. Thus the digital value after correction issubstantially equal to the analog value at the output of thedigital-to-analog converter.

In one advantageous variant of the invention, said predetermined valueis equal to zero and, during the calibration phase, and during theperiod P1 _(i) for each level X_(i), the number N_(i) of values equal toX_(I) and the total number NT_(i) of all the output values are countedat the output of the sigma-delta analog-to-digital converter and a sumS1 _(i) of the NT_(i) values is calculated. The periods P1 _(i), whichare not all equal a priori, can depend on each intermediate level X_(i).In this case, step F of the calibration phase is executed N−2 times,each time taking a period P2 _(i) equal to each period P1 _(i), and asum S2 _(i) is calculated of all the values leaving the sigma-deltaanalog-to-digital converter during each execution, after which acorrection value C_(i) corresponding to the value X_(i) is calculatedfrom the equation (for i from 1 to N−2):$C_{i} = \frac{{S2}_{i} - {S1}_{i}}{N_{i}}$

The period P1 _(i) for each level X_(i) is preferably equal to theperiod needed to count the number N_(i) of values equal to X_(i) at theoutput of the sigma-delta analog-to-digital converter (A2) until thenumber N_(i) is equal to a given number N₀.

If step F is executed only once (in which case all the periods P1 _(i)are equal to each other and to P2), there is only one sum S2 and Ci canbe calculated from the following equation (for i from 1 to N−2):$C_{i} = \frac{{S2} - {S1}_{i}}{N_{i}}$

There are various ways to calculate the correction values Ci.

The invention also proposes a system for compensating the non-linearityof a sigma-delta analog-to-digital converter with N quantizing levelsincluding a digital-to-analog converter and a digital filter. Accordingto a general feature of the invention, the system includes means forimplementing the various phases previously described.

In a preferred embodiment, the calculating and modifying means include:

counter means for counting the values leaving the sigma-deltaanalog-to-digital converter,

at least one accumulator for summing the values leaving the sigma-deltaanalog-to-digital converter,

storage means for memorizing numbers delivered by the counting means andthe accumulator,

processor means for performing calculations on the memorized numbers andgenerating control signals in the system for controlling the variousphases,

a correction module between the quantizer and the digital filter andcommunicating with the processor means, and

comparators and a digital processor module internal to the N-levelquantizer and capable of converting the quantizer into a quantizer withfewer than N quantizing levels.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features of the invention will become apparent onexamining the detailed description of one non-limiting embodiment andthe accompanying drawings in which:

FIG. 1 depicts a prior art sigma-delta analog-to-digital converter.

FIG. 2 is a prior art depiction of components employed in a calibrationphase of a sigma-delta analog-to-digital converter.

FIG. 3 depicts a prior art adder using switched capacitors.

FIG. 4 depicts a diagram of the general structure of a sigma-deltaanalog-to-digital converter implementing the invention.

FIG. 5 depicts a diagrammatic view of a three-level quantizerimplementing the invention.

FIGS. 6a and 6 b depict the results of converting a five-level quantizerinto a three-level quantizer.

Although the invention is not limited to it, one example of the methodand the system according to the invention for compensating thenon-linearity of a sigma-delta analog-to-digital converter with threequantizing levels will now be described.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The FIG. 4 diagram is in three parts. A first part A1 relates to theinput signals, a second part A2 relates to the sigma-deltaanalog-to-digital converter itself, and a third part A3 relates to acontrol system.

The first part A1 has a zero value input 15 used during a calibrationphase and an input 16 receiving the analog signal to be digitized by thesigma-delta analog-to-digital converter. A switch 17 connects either tothe input 15 or to the input 16.

In the second part A2, a signal from the input 15 or 16 reaches thepositive input 18 a of an adder 19. A noise-shaping filter 20 recoversthe output signal of the adder 19. The signal 21 leaving thenoise-shaping filter 20 is fed to the input of a quantizer 22 with threequantizing levels: −1, 0 and 1. The quantizer 22 generates a digitalsignal 23 which, during a normal operation phase, is fed to the input ofa corrector module 27 via a switch 26. The output signal of thecorrector module 27 is then passed through a digital filter 28 in orderto undersample it. Undersampling reverts to a frequency in the vicinityof the Nyquist frequency. The digital signal 23 also passes through afeedback loop 25 including a digital-to-analog converter 24 whose outputsignal is fed to the negative input 18 b of the adder 19.

The third part A3 is a control device including an accumulator 29, acounter 30 and a second counter 31, all three of which are connected toa random access memory module 32 connected to a digital processor module33. The digital processor module 33 performs calculations and generatesdata signals 35 that are sent to the corrector module 27 of thesigma-delta analog-to-digital converter and control signals 34 that aresent to the quantizer 22 and the switches 17 and 26.

In normal operation, the digital-to-analog converter 24 receives threedifferent digital values (for example in the form of pairs of bits 01,00 and 10 coding the values −1, 0 and 1), and converts them into threeanalog values, which should ideally be −1, 0 and 1.

The three analog points do not usually correspond ideally to the values−1, 0 and 1. For example, the analog point leaving the digital-to-analogconverter whose ideal value is 0 can be corrected. The correction of the0 point is independent of the zero value at the input 15. It is possibleto correct the +1 and −1 points with the zero value still present at theinput 15.

During the first calibration phase the switch 17 is switched to the zerovalue input 15 and the switch 26 is switched to an input 36 common tothe accumulator 29, the counter 30 and the second counter 31. Thequantizer 22 operates in a three-level quantizing mode. The counter 31then counts the number N₀ of 0 points (points to be corrected) containedin the digital signal 23 passing from the input 36 to the counter 31.The count continues until the number N₀ reaches a predetermined value.To facilitate subsequent calculations the predetermined value is a powerof two. It is equal to 2¹⁸, for example, i.e. to 262 144.

The accumulator 29 calculates the sum S1 of the values of the outputsignal of the quantizer 22. The sum S1 is stored in the random accessmemory 32, together with the number N₁ of points generated by thequantizer 22 and counted by the second counter 30. The value 2¹⁸ ischosen so that it is sufficiently large for the values stored in memoryto be accurate.

The second calibration phase consists of converting the sigma-deltaanalog-to-digital converter with three quantizing levels into asigma-delta analog-to-digital converter with two quantizing levels. Forthis it suffices to convert the three-level quantizer 22 into atwo-level quantizer. The two levels are the −1 and +1 points. The switch17 is still switched to the input 15 and the switch 26 is still switchedto the input 36. During this phase the sigma-delta analog-to-digitalconverter is operated with zero at the input during N₁ samples. Theaccumulator 29 also calculates the sum S2 of the N₁ output samples. Azero point correction value is finally calculated from the equation:

C=(S 2−S 1)/N ₀

The division is simple to effect in the digital processor module 33because a power of two has been chosen for the value of N₀. The value Cis then saved in the memory 32, which has three compartments in which itsaves the number N₁, the sum S1 and the value C.

Once these two calibration phases have been completed, the phase ofnormal operation of the sigma-delta analog-to-digital converter withthree quantizing levels begins. The switch 17 is switched to the input16, the switch 26 is switched to the corrector module 27, and thequantizer 22 operates with three quantizing levels −1, 0 and +1. Theanalog signal to be digitized is fed to the input 16 and leaves thequantizer 22 in the form of a digital signal 23 which is modified by thecorrector module 27 and then digitally filtered by the module 28. Thecorrector module 27 executes an algorithm that can be summarized as inthe table below:

input output  1  1  0 0 + C −1 −1

Thus if the digital value 0 is present at the output of the quantizer22, it is replaced by its correction value C at the output of thecorrector module 27.

FIG. 5 shows the three-level quantizer 22 made up of two comparators 37and 38 and a digital processor module 39. The comparator 37 has twoinputs, a first of which receives the signal 21 from the noise-shapingfilter 20 and the second of which is maintained at a fixed voltage Vequal to a positive quantizing threshold voltage. The comparator 38 alsohas two inputs, the first of which also receives the signal 21, and thesecond input of the comparator 32 is maintained at a voltage equal to−V. The output of the comparator 37 and that of the comparator 38 enterthe digital processor module 39 generating the digital output signal 23.If the value of the input signal 21 is greater than V, the digitalsignal 23 takes the value +1. If the value of the input signal 21 isless than −V, the signal 23 takes the value −1. If the value of theinput signal 21 is between −V and V, the signal 23 is equivalent to 0.The digital processor module 39 is governed by the following algorithm,in which S₃₇ is the output of the comparator 37, and S₃₈ is the outputof the comparator 38: +1 = S₃₇$0 = {{\overset{\_}{S_{37}} - S_{38} - 1} = \overset{\_}{S_{38}}}$

To convert the three-level quantizer 22 into a two-level quantizer thevalues V and −V at the second inputs of the comparators 37 and 38 arereplaced by a null value and the algorithm of the digital processormodule 39 is modified so that, when the value of the input signal 21 ispositive, the signal 23 is equivalent to +1 and, when the value of theinput signal 21 is negative, the signal 23 is equivalent to −1. To thisend, the algorithm of the digital processor module 39 is as follows:${+ 1} = {{S_{37} - 1} = \overset{\_}{S_{37}}}$

In fact, only the comparator 37 is used, the comparator 38 beingrendered “invisible”.

The non-linearity of the sigma-delta analog-to-digital converterdescribed above can be compensated by carrying out a calibration phasewithout modifying the structure of the sigma-delta analog-to-digitalconverter.

FIGS. 6a and 6 b show the conversion of the five-level quantizer into athree-level quantizer. The E axis represents the input signal 7 and theS axis represents the output signal 9. FIG. 6a shows the transferfunction of a five-level quantizer (−1; −0.5; 0; 0.5; 1). For example,any input signal having a value between two positive values v1 and v2delimiting a range of values on the E axis is converted into a digitalsignal of value equal to 0.5 on the S axis. To correct the zero level byconverting the quantizer to three levels, the intermediate levels (−0.5and 0.5) are eliminated, as shown in FIG. 5b. The remaining three levelsare therefore (−1; 0; 1).

For example, in a simulation for a signal to be converted of maximumamplitude and no correction in accordance with the invention, asigma-delta analog-to-digital converter with three quantizing levelssampled at a frequency of 2 048 kHz had a signal/noise ratio of 46 dB.The results obtained after applying the first calibration phase withN₀=262 144 were as follows: N₁=372 522 and S1=−6 408.

Executing the second calibration phase yielded a sum S2=−3 116 and a 0point correction value C such that:

C=(S 2−S 1)/N ₀=3 292/262 144

A signal/noise ratio of 105 dB was then obtained in normal operation fora signal to be converted of maximum amplitude and with correction inaccordance with the invention.

The method described above performs a calibration phase using athree-level quantizer and then a two-level quantizer but retains thegeneral structure of the sigma-delta analog-to-digital converter. Thecalibration phase is effected simply by controlling the variousswitches.

What is claimed is:
 1. A method of compensating the non-linearity of asigma-delta analog-to-digital converter with N quantizing levels andincluding a digital-to-analog converter in a feedback loop, comprising:a normal operation phase in which a plurality of digital valuescorresponding to a plurality of quantizing levels are modified bycorrection values C_(i), where i is a positive integer from 1 to N; anda calibration phase in which the correction values C_(i) are calculatedfrom values of the output of the sigma-delta analog-to-digital converterprocessed digitally with the digital-to-analog converter retained in thefeedback loop of the sigma-delta analog-to-digital converter and afterconverting the multibit sigma-delta analog-to-digital converter into asigma-delta analog-to-digital converter with three quantizing levels;wherein during the calibration phase the multibit sigma-deltaanalog-to-digital converter is converted into a sigma-deltaanalog-to-digital converter with three quantizing levels X_(m), X_(M),and X_(i), where i is from 1 to N−2; wherein during a period P1 _(i), apredetermined value is delivered to the input of the sigma-deltaanalog-to-digital converter and the values from the output of thesigma-delta analog-to-digital converter are processed digitally; whereinthe calibration phase is executed N−2 times, retaining the levels X_(m)and X_(M), and taking successively for the level X_(i), the N−2 levelsother than the levels X_(m) and X_(M); and wherein the correction valuesC_(i) of the N−2 levels other than X_(m) and X_(M) are calculated usinga sum of the processed values, the N−2 correction values C_(i) beingadapted to modify the N−2 levels other than X_(m) and X_(M) during thenormal operation phase.
 2. The method of claim 1, further comprisingduring the calibration phase and before calculating the correctionvalues C_(i), at least one step F during which the multibit sigma-deltaanalog-to-digital converter is converted into a sigma-deltaanalog-to-digital converter with two quantizing levels X_(m) and X_(M),during a period P2, wherein the predetermined value is delivered to theinput of the sigma-delta analog-to-digital converter and the successivevalues of the output of the sigma-delta analog-to-digital converter areprocessed digitally.
 3. The method of claim 2, wherein the sigma-deltaanalog-to-digital converter with N quantizing levels is converted into asigma-delta analog-to-digital converter with a number of quantizinglevels less than N by modifying quantizing threshold values and bydigital processing using internal comparators.
 4. The method of claim 3,wherein during the normal operation phase, the correction value C_(i) isadded to each level X_(i) present at the output of the quantizer.
 5. Themethod of claim 4, wherein step F of the calibration phase is executedN−2 times, each time taking a period P2 _(i) equal to each period P1_(i), and a sum S2 _(i) is calculated of all the values leaving thesigma-delta analog-to-digital converter during each execution, afterwhich a correction value C_(i) corresponding to the value X_(i) iscalculated from the equation: C_(i)=(S2 _(i)−S1 _(i))/N_(i).
 6. Themethod of claim 5, wherein the period P1 _(i), for each level X_(i), isequal to the period needed to count the number N_(i) of values equal toX_(i) at the output of the sigma-delta analog-to-digital converter untilthe number N_(i) is equal to a given number N₀.
 7. The method of claim3, wherein the predetermined value is equal to zero, and wherein duringthe calibration phase and during the period P1 _(i) for each levelX_(i), the number N_(i) of values equal to X_(i) and the total numberNT_(i) of all the output values are counted at the output of thesigma-delta analog-to-digital converter and a sum S1 _(i) of the NT_(i)values is calculated.
 8. The method of claim 7, wherein the period P1_(i), for each level X_(i), is equal to the period needed to count thenumber N_(i) of values equal to X_(i) at the output of the sigma-deltaanalog-to-digital converter until the number N_(i) is equal to a givennumber N₀.
 9. The method of claim 3, wherein the levels X_(m) and X_(M)are respectively the minimum value and the maximum value of the Nquantizing levels.
 10. The method of claim 2, wherein the levels X_(m)and X_(M) are respectively the minimum value and the maximum value ofthe N quantizing levels.
 11. The method of claim 2, wherein during thenormal operation phase, the correction value C_(i) is added to eachlevel X_(i) present at the output of the quantizer.
 12. The method ofclaim 2, wherein the predetermined value is equal to zero, and whereinduring the calibration phase and during the period P1 _(i) for eachlevel X_(i), the number N_(i) of values equal to X_(i) and the totalnumber NT_(i) of all the output values are counted at the output of thesigma-delta analog-to-digital converter and a sum S1 _(i) of the NT_(i)values is calculated.
 13. The method of claim 1, wherein the levelsX_(m) and X_(M) are respectively the minimum value and the maximum valueof the N quantizing levels.
 14. The method of claim 1, wherein duringthe normal operation phase, the correction value C_(i) is added to eachlevel X_(i) present at the output of the quantizer.
 15. The method ofclaim 1, wherein the predetermined value is equal to zero, and whereinduring the calibration phase and during the period P1 _(i) for eachlevel X_(i), the number N_(i) of values equal to X_(i) and the totalnumber NT_(i) of all the output values are counted at the output of thesigma-delta analog-to-digital converter and a sum S1 _(i) of the NT_(i)values is calculated.
 16. A system for compensating the non-linearity ofa sigma-delta analog-to-digital converter with N quantizing levels,comprising: a digital-to-analog converter in a feedback loop and adigital filter, wherein the digital-to-analog converter comprises meansfor calculating correction values C_(i), where i is a positive integerfrom 1 to N, during a calibration phase and from values of the output ofthe sigma-delta analog-to-digital converter processed digitally with thedigital-to-analog converter retained in the feedback loop of thesigma-delta analog-to-digital converter and by converting the multibitsigma-delta analog-to-digital converter into a sigma-deltaanalog-to-digital converter with three quantizing levels, and means formodifying a plurality of digital values corresponding to a plurality ofquantizing levels by applying the correction values C_(i) during anormal operation phase; wherein the calculating and modifying meanscomprise: counter means for counting the values leaving the sigma-deltaanalog-to-digital converter; at least one accumulator for summing thevalues leaving the sigma-delta analog-to-digital converter; storagemeans for memorizing numbers delivered by the counting means and theaccumulator; processor means for performing calculations on thememorized numbers and generating control signals in the system forcontrolling the various phases; a correction module between thequantizer and the digital filter, communicating with the processormeans; and comparators and a digital processor module internal to theN-level quantizer and capable of converting the quantizer into aquantizer with fewer than N quantizing levels.
 17. A method ofcompensating the non-linearity of a sigma-delta analog-to-digitalconverter with N quantizing levels and including a digital-to-analogconverter in a feedback loop, comprising: a normal operation phase inwhich a plurality of digital values corresponding to a plurality ofquantizing levels are modified by correction values C_(i), where i is apositive integer from 1 to N; and a calibration phase in which thecorrection values C_(i) are calculated from values of the output of thesigma-delta analog-to-digital converter processed digitally with thedigital-to-analog converter retained in the feedback loop of thesigma-delta analog-to-digital converter and after converting themultibit sigma-delta analog-to-digital converter into a sigma-deltaanalog-to-digital converter with three quantizing levels; wherein duringthe calibration phase the multibit sigma-delta analog-to-digitalconverter is converted into a sigma-delta analog-to-digital converterwith three quantizing levels X_(m), X_(M), and X_(i), where i is from 1to N−2; wherein during a period P1 _(i), a predetermined value isdelivered to the input of the sigma-delta analog-to-digital converterand the values from the output of the sigma-delta analog-to-digitalconverter are processed digitally; wherein the calibration phase isexecuted N−2 times, retaining the levels X_(m) and X_(M), and takingsuccessively for the level X_(i), the N−2 levels other than the levelsX_(m) and X_(M); and wherein the correction values C_(i) of the N−2levels other than X_(m) and X_(M) are calculated using the processedvalues, the N−2 correction values C_(i) being adapted to modify the N−2levels other than X_(m) and X_(M) during the normal operation phase. 18.The method of claim 17, further comprising during the calibration phaseand before calculating the correction values C_(i), at least one step Fduring which the multibit sigma-delta analog-to-digital converter isconverted into a sigma-delta analog-to-digital converter with twoquantizing levels X_(m) and X_(M), during a period P2, wherein thepredetermined value is delivered to the input of the sigma-deltaanalog-to-digital converter and the successive values of the output ofthe sigma-delta analog-to-digital converter are processed digitally.